1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus having a photoelectric conversion element and a capacitor element for holding a signal, a contact-type image sensor, and an original image reading apparatus. The contact-type image sensor uses plural photoelectric conversion apparatuses mounted thereto to read an original image by receiving light reflected by an original surface to be read.
2. Related Background Art
FIG. 14 is a schematic diagram of a conventional photoelectric conversion apparatus.
In FIG. 14, a circuit of a 6-pixel linear sensor is shown as an example. The respective pixels are arranged in line. Reference numeral 1 denotes a photoelectric conversion element such as a photodiode; a hole storage type photodiode is used by way of example herein (note that the photoelectric conversion element 1 is assigned with sub-numbers like 1-1, 1-2, . . . for each pixel; the same applies to other elements in the following description). Reference numeral 2 denotes a first reset MOS transistor; 3, an input MOS transistor of a first source follower; and 4, a constant current source of the first source follower. The input MOS transistor 3 and the constant current source 4 constitute a first source follower 5. In FIG. 14, a source follower configured by a PMOS transistor is shown by way of example. Reference numeral 6 denotes a first transfer MOS transistor (an NMOS transistor is used herein as an example); 7, a first storage capacitor; 8, an input MOS transistor of a second source follower; and 9, a constant current source of the second source follower. The input MOS transistor 8 and the constant current source 9 constitute a second source follower 10. In FIG. 14, a source follower configured by a PMOS transistor is shown by way of example. Reference numeral 11 denotes a second transfer MOS transistor; 12, a second storage capacitor; 13, a third transfer MOS transistor; 14, a third storage capacitor; 15, a scanning circuit; 16, a fourth transfer MOS transistor driven with a signal from the scanning circuit 15; 17, a common output line commonly connected with one terminal of the fourth transfer MOS transistor 16; 18, a differential-input output amplifier connected with the common output line 17; 19, a second reset MOS transistor for resetting the common output line 17; 20, a logic circuit for generating a pulse for controlling an operation of each of the reset MOS transistors and transfer MOS transistors; 21, a first reset power source; and 22, a second reset power source.
FIG. 15 shows an operational timing of the circuit.
Referring to FIG. 15, a circuit operation is described in brief. Reference symbol PRES denotes a reset pulse input to a gate of the reset MOS transistor 2; PCM, a first transfer pulse input to a gate of the first transfer MOS transistor; PTN, a second transfer pulse input to a gate of the second transfer MOS transistor 11; PTS, a third transfer pulse input to a gate of the third transfer MOS transistor 13; SR1 to SR6, scanning pulses sequentially output from the scanning circuit 15; and PRES2, a second reset pulse input to a gate of the second reset MOS transistor 19. Reference symbol VSF1 denotes an output terminal potential of the first source follower 5; VM, a potential of the first storage capacitor 7; VN, a potential of the second storage capacitor 12; VS, a potential of the third storage capacitor 14; and VOUT, an output terminal potential of the output amplifier 18.
First, the first reset MOS transistor 2 is turned on in response to the reset pulse “PRES” at time to, thereby resetting the photoelectric conversion element 1. After that, the first transfer MOS transistor 6 is turned on in response to the first transfer pulse “PCM” at time t1, thereby transferring the reset voltage to the first storage capacitor 7 through the first source follower 5. The first transfer MOS transistor 6 is turned off at time t2 to hold the reset voltage in the first storage capacitor 7. The photoelectric conversion element 1 starts an operation of accumulating optical signals to generate signal charges in accordance with an incident light amount. The generated signal charges are converted into a signal voltage with a capacitor (not shown) provided in a position where the photoelectric conversion element 1 and the first input MOS transistor 3 are connected with each other.
In general, the capacitance corresponds to a junction capacitance of a photodiode, a drain junction capacitance of the reset MOS transistor, a gate capacitance of the input MOS transistor, and an inter-connection-wiring capacitance. Alternatively, the capacitance may be an intentionally added one. The second transfer MOS transistor 11 is turned on in response to the second transfer pulse “PTN” at time t3, transferring the reset voltage across the storage capacitor 7 through the second source follower 10 to the second storage capacitor 12. The second transfer MOS transistor 11 is turned off at time t4 to hold the reset voltage in the second storage capacitor 12.
Next, the first transfer MOS transistor 6 is turned on again in response to the first transfer pulse “PCM” at time t5 that is an end time of accumulation operation, transferring the signal voltage through the first source follower 5 to the first storage capacitor 7. The first transfer MOS transistor 6 is turned off at time t6 to hold the signal voltage in the storage capacitor 7. Following this, the third transfer pulse “PTS” is input at time t7 to turn the third transfer MOS transistor 13 on, transferring the signal voltage across the first storage capacitor 7 to the third storage capacitor 14. The third transfer MOS transistor 13 is turned off at time t8 to hold the signal voltage in the third storage capacitor 14. The photoelectric conversion element 1 is reset again by turning the first reset switch on in response to the reset pulse “PRES” at time t9 and then starts accumulating optical signals in the next field. In parallel therewith, the common output line is reset in response to turn-on of the second reset pulse “PRES2”. After this reset, the fourth transfer MOS transistor 16 is turned on in response to the scanning pulse SR1 to read the reset voltage and the signal voltage across the storage capacitors 12 and 14 to the common output line 17. A voltage difference between the two voltages is output as “VOUT” through the output amplifier 18 of the differential input.
Hereinafter, the reset pulse “PRES2” and the scanning pulses “SR2” to “SR6” are sequentially turned on to sequentially read signals of the 6-pixel linear sensor. Using the read circuit as in this example makes it possible to perform the optical signal accumulating operation in the photoelectric conversion element portion concurrently with the signal reading operation. Therefore, a high-speed operation is realized.
FIGS. 16A to 16C schematically show the peripheral of the first transfer MOS transistor 6 of FIG. 14.
In FIGS. 16A to 16C, the same members as those in FIG. 14 are denoted by like reference symbols. FIG. 16A shows a case where all the transfer MOS transistors are turned on, FIG. 16B shows a case where some of the transfer MOS transistors are turned on, and FIG. 16C shows a case where all the transfer MOS transistors are turned off. Reference numeral 301 denotes a gate of the transfer MOS transistor 6; 302, a source of the transfer MOS transistor 6; 303, a drain of the transfer MOS transistor 6; and 304, a channel region formed below the gate 301 through a gate insulating film with the transfer MOS transistor 6 is turned on. A well region underlies the channel region 304. Reference numeral 305 denotes a capacitor between the gate 301 and the source 302; 306, a capacitor between the gate 301 and the drain 303; 307, a capacitor formed between the gate 301 and the channel 304 when the transfer MOS transistor 6 is turned on; 308, a capacitor formed between the gate and the well when the transfer MOS transistor 6 is turned off; 309, a resistance component added between the source follower 5 and the storage capacitor 7; 310, a control line for driving the gate of the first transfer MOS transistor 6; and 311, a resistance component involved in the control line which is schematically shown. The resistance component 309 corresponds to an internal resistance of the source follower and a channel resistance of the first transfer MOS transistor 6. Also, the resistance component 311 corresponds to a wiring resistance of the control line.
The capacitance involved in the control line corresponds to the capacitors 305, 306, and 307 when the transfer MOS transistor 6 is turned on as shown in FIG. 16A, and to the capacitors 305, 306, and 308 when the transistor is turned off as shown in FIG. 16C. The capacitor 308 is a series capacitor of a capacitor of the gate insulating film and a depletion layer capacitor of the well. Thus, its capacitance value is smaller than that of the capacitor 307. Thus, the capacitance involved in the control line takes a larger value when the transfer MOS transistor 6 is turned on than a value when the transistor is turned off.
Here, the operation of the transfer MOS transistor 6 at time t2 in FIG. 15 will be discussed in more detail. As shown in FIG. 16A, when the gate voltage level is high, all the transfer MOS transistors 6 are turned on, so the capacitors 305, 306, and 307 of all the transfer MOS transistors 6 function as loads on the control line. Then, when the gate voltage gradually lowers in the course of the off-operation starting form the time t2 down to a voltage whose difference from the source voltage approximates to a threshold voltage, the transfer MOS transistor 6 is turned off. Thus, as shown in FIG. 16C, the capacitance involved in the control line is reduced as mentioned above. At the time t2, the photoelectric conversion element has just been reset, so the source of all the transfer MOS transistors 6 reaches a potential substantially corresponding to a reset voltage. As a consequence, all the transfer MOS transistors 6 are switched from an on-state to an off-state at substantially the same timing.
Next, FIGS. 17A and 17B are detailed charts showing timings of the operation at the time t2 of FIG. 15.
FIG. 17A shows a gate voltage change with time of the transfer MOS transistor 6. In FIG. 17A, during a T1 period, the large capacitance is involved in the control line, so a gate voltage gradient is gentle as shown in FIG. 17A due to an RC time constant resulting from the resistor 311 and the capacitor of the control line. When the gate voltage is gradually lowered to turn the transfer MOS transistor 6 off as mentioned above, the capacitance involved in the control line is reduced, with the result that the gate voltage changes abruptly (see a period T3). FIG. 17B shows a change of the potential “VM” across the first storage capacitor 7 connected to the transfer MOS transistor 6. The first storage capacitor 7 and the control line 310 are coupled with the capacitors 305, 306, and 307 as shown in FIG. 16A. If the resistance with the source follower 5 is small enough, the voltage across the storage capacitor 7 can be fixed to the output voltage of the source follower. In practice, there is the resistance component 309, so the potential of the storage capacitor is transitionally changed in accordance with a change of the potential of the control line. The transitional change in potential is fixed when the transfer MOS transistor 6 is turned off. This change corresponds to a shift from a voltage to be basically read and output to the storage capacitor 7.
As shown in FIG. 17B, the voltage across the storage capacitor 7 is changed in accordance with how much the gate voltage is changed during the period T1. The transfer MOS transistor is turned off during the period T3 to thereby fix the transient potential change caused when in on-state. In addition, the storage capacitor 7 stays coupled with the control line through the capacitor 306, whereby the potential of the storage capacitor 7 changes.
Referring to FIGS. 17C and 17D, the operation at time t6 of FIG. 15 is more detailed. At this time, the photoelectric conversion elements 1-1 to 1-3 of FIG. 14 receive irradiated light, and the elements 1-4 to 1-6 are in a dark state. With that proviso, all the transfer MOS transistors 6 are turned on during the period T1 of FIG. 17C, so the gate voltage is changed at the same change rate as that in the period T1 of FIG. 17A. Similarly, the voltage across the storage capacitor 7 is changed as shown in FIG. 17D in the same way. Next, description is directed to the period T2. The output voltage from the source follower 5 in pixels connected to the photoelectric conversion element irradiated with light is higher than that of the pixels in a dark state. Thus, the transfer MOS transistors 6-1 to 6-3 of the irradiated pixels are first turned off. FIG. 16B shows a state during the period T2 in which three of the six pixels are turned off and the remaining three are turned on. As apparent from FIG. 16B, the capacitance involved in the control line corresponds to a capacitance value between the period T1 and the period T3. Hence, the voltage of the control line changes with the angle of gradient intermediate between that of the period T1 and that of the period T3. Therefore, as shown in FIG. 17D, the potential change rate of the storage capacitor 7 in each pixel in a dark state is different from that of FIG. 17B depending on the potential change rate in the period T2.
Here, the pixels connected with the photoelectric conversion elements 1-4 to 1-6 have not been irradiated with light, so the potentials of the storage capacitor 7 are supposed to be the same at the time t2 and the time t6 and the output of the differential output amplifier 18 is 0. However, as mentioned above, there is a difference in potential of the storage capacitor 7 between the time t2 and the time t6 depending on the amount of light applied to the other photoelectric conversion elements 1-1 to 1-3. As a result, the output amplifier 18 of FIG. 14 will output a signal of a negative value. Thus, the signal whose level is lower than a level originally preset for a dark state is output, whereby a corresponding portion on the image is displayed in black beyond expectations, leading to a deteriorated image quality.
FIGS. 18A to 18C schematically show the above-mentioned contact-type image sensor configured by mounting the plural photoelectric conversion apparatuses thereto.
The contact-type image sensor is disclosed in, for example, Japanese Patent Application Laid-Open No. H11-234473. In FIG. 18A, reference numeral 401 denotes individual photoelectric conversion apparatuses; 402, a photoelectric conversion element; and 403, a peripheral processing circuit part in the photoelectric conversion apparatus. In FIG. 18A, the contact-type image sensor 404 including three photoelectric conversion apparatuses having 6 pixels is shown by way of example. FIG. 18B shown below FIG. 18A is a chart illustrative of a conventional photoelectric conversion apparatus with an output from the photoelectric conversion apparatus represented by the vertical axis, and spatial arrangement of corresponding pixels represented by the horizontal axis.
Here, consider the case in which preceding three pixels of the photoelectric conversion apparatus 401-1 are irradiated with light, and the rest are brought into a dark state. The preceding three pixels “a” to “c” of the photoelectric conversion apparatus 401-1 output signals corresponding to an irradiated light amount. The remaining three pixels “d” to “f” output signals of a negative value that becomes larger in the order of “d”, “e”, and “f” owing to a potential change of the storage capacitor as mentioned above. However, the photoelectric conversion apparatuses 401-2 and 401-3 have not received irradiated light at every pixel thereof, so such signals of a negative value are not output. Accordingly, it is necessary to output signals corresponding to the dark state from the sixth pixel “f” of the photoelectric conversion apparatus 401-1 and the first pixel “a” of the photoelectric conversion apparatus 401-2. Howbeit, one of them outputs the signal of a large negative value, so the boundary therebetween is recognized as a step, leading to a much larger deterioration in image quality than that with a single photoelectric conversion apparatus.